DVCC based Readout Circuitry for Water Quality Monitoring System

Abstract

new configuration realizing water quality monitoring device using ISFET involving CMOS differential voltage current conveyor (DVCC) based low pass filter free from trans-conductance variation using Low-voltage PMOS bulk- driven cascade current mirror (P MOS BDCCM) current mirrors is proposed. The circuit uses four DVCCs as active elements and together with two capacitors and five resistors as passive elements, only one current mirror. The use of this active component makes the implementation simple and attractive. The functionality of the circuit is tested using Tanner simulator version 15 for a 70nm CMOS process model also the transfer function realization is done on MATLAB R2011a version, the Very high speed integrated circuit Hardware description language(VHDL) code for the same scheme is simulated on Xilinx ISE 10.1 and various simulation results are obtained. Simulation results are included to demonstrate the results. OTA's. These applications are suffer from low band widths (BW's) arising due to stray and circuit capacitances. Also the need for low voltage, low power circuits makes these circuits not suitable for water quality monitoring as these circuits required the minimum bias voltage depends on the threshold voltage of the MOSFETs. However, with the advancement in the analog VLSI new analog devices are based on currents are developed called current mode circuits (CMC's). These circuits have a significant advantage of low power, low voltages and can operate over wide dynamic range. These circuits, CMC can offer to the designer large bandwidths, greater linearity, wider dynamic range, simple circuitry and low power consumption. Current feedback op-amps (CFOAs), operational floating conveyors (OFCs) and current conveyors (CCs) etc. are popular CMC configuration and most widely used structure among them is DVCC, extension of the second- generation current conveyor (CCII). Hence, we decided to use the DVCC in the proposed scheme.