DUST ACOUSTIC SOLITARY AND SHOCK WAVES WITH NON-THERMAL IONS IN DUSTY PLASMA HAVING DUST CHARGE FLUCTUATION

Abstract

In digital circuits designing the SRAM design constraints are very important. In the integrated circuits fabrication the majority of space is taken by the memories.. The design considerations of SRAM consist of: increased speed and reduced power. CMOS devices are shrinking to nanometer regime, thereby, increasing short channel effects and process parameter variations that degrades the reliability of the circuit as well as performance. To solve these issues of CMOS, FinFET proves to be better technology, without sacrificing reliability and performance for its applications and the circuit design. The use of FinFETs, transmission gates are used in the access path of the SRAM Cell and the Sleep transistors power gating technique are used for low leakage power and high performance. The transient and dc analysis of the proposed ST11T, ST13T and with sleep transistors SRAM cell has been obtained using Cadence Virtuoso tool and BSIMCMG model 107.0.0 for 22nm FinFETs to achieve high performance. It can be observed from the results that the percentage improvement of 97.30% in power dissipation, 27.77% in delay, 98.05% in PDP and 38.37% increase in speed is obtained for the proposed finFET-based ST13T circuit with power gating technique are that shows the high performance for SRAM Cell as compared to design based on CMOS technology. Keywords : CMOS Integrated Circuit, Integration VLSI, Layout, Memory Design, FinFET devices, SRAM Chips.