Dual V<inf>dd</inf> and multi V<inf>th</inf> cascaded inverters as level converter for clock distribution network

Abstract

As Integrated Circuits are more complex, the need of supplying accurate and synchronized clocks to all the circuits becomes increasingly difficult. In some cases, more than one clock cycle is required to perform a predictable action. Clock Circuits are responsible for proportionate fraction of the power dissipation of a chip and are important in terms of performance. In integrated circuit, multiple supply voltages are utilized for reducing the power consumption by a sub-circuit. A sub circuit supply voltage is used to generate an output signal at a Lower Supply Voltage for another sub circuit and is generated from a higher supply voltage, and this achieves reduction of the power consumption by the sub circuit. Since an output signal generated by the sub circuit is a lower voltage signal, at the front stage of an output circuit, a level conversion circuit transform the level of this signal into a signal for the higher external supply voltage and Vice versa. In this paper for high performance and Low power design, two different types of level converters are proposed and the effect of temperature on process parameters is analyzed using Cadence Tools.