Dual‐rail improved adiabatic pseudo‐domino logic with auxiliary clock: a low‐power partially‐adiabatic CMOS logic family

Abstract

An improved structure for adiabatic pseudo‐domino logic (APDL) family is presented in this paper. The modified dual‐rail improved APDL (MDIAPDL) exhibits lower power dissipation than the conventional static CMOS as shown in HSpice simulations. Comprehensive circuit simulations show that the MDIAPDL 4 bit shift register can recover over 95 per cent of the energy dissipated in conventional static CMOS 4 bit shift register.