Abstract
Proper control of the voltage applied at both gates of a planar dual-gate field effect transistor (FET) using a cellulose matrix as the dielectric makes it possible to operate them either in depletion or enhancement mode. In article number 1800423, Luís Pereira, Elvira Fortunato, Rodrigo Martins, and co-workers demonstrate the implementation of universal logic gates (NAND and NOR) using only one transistor, by setting the appropriate combination of the voltage level applied at each gate.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
