Dual Die Processor Package Design Optimization and Performance Evaluation

Abstract

The quest for higher performance in microprocessors has steered the industry towards multi-core architectures which has significantly increased the challenges in silicon-package integration. In the past, designers have exploited parallelism through hyper threading (HT) technology where the operating system sees one physical processor as two logical processors. Even though HT simulates dual processing, the performance gain from HT is limited to applications that don't utilize same processor resources. For example if an application generates two floating point intensive threads, the execution of these threads would need to alternate with the single floating point unit and in most cases this would result in performance slow down. To address this problem, an integration of multiple dies to increase processor resources namely level1/level2 cache, registers, floating point units etc., is warranted so the execution of the threads can be done in parallel. Although this configuration is scalable and improves performance, adds considerable package design challenges to generate optimized solutions.