DSP Algorithms for On-Board Satellite Transmultiplexer and Receiver

Abstract

This paper presents computationally efficient algorithms for a Digital Signal Processor (DSP) implementation of transmultiplexers, timing and carrier recovery, and detection of data for on-board satellite receiver. The transmultiplexer which generates a time domain sequence of a Frequency Division Multiplexed (FDM) signal is implemented using DFT filter banks. Carrier and timing recovery and data detection are implemented assuming no training sequence. It is very important to design efficient algorithms to perform these tasks so that computational requirements are kept to a minimum thereby saving power.The paper proposes a novel 4th power based algorithm to determine the carrier offset. It is based on the idea that if there are P samples per symbol, then one of them is closer to the ideal Nyquist sampling instant than others, and, has the least ISI. A recursive method to isolate this minimum-ISI sample is proposed. This sample is used to estimate the carrier phase. Since the method identifies the least ISI sequence, it is said to perform both the carrier and timing offset estimation. After compensating for constant frequency offset, timing recovery is performed using a modified Peak Average Energy Criterion (PAEC) algorithm. A Digital Phase Locked Loop (DPLL) is used to track the finer variation in frequency offset.Results of simulations evaluating performance of these algorithms are presented for a number of frequency and timing offset situations. It is seen that the computational load is maximum at “start-up”. We have proposed a particular start-up scheme and calculated its peak computational load in Millions of Instructions per second (MIPs).