Abstract

This paper proposes an efficient encryption technique based on Dynamic and Secure Substitution Box (DS2B) design suitable for IoT and resource-constrained platforms. The DS2B has the advantages of simple structure and good encryption performance. A different number of strong S-boxes could be generated with minor variations in the DS2B parameters. Performance analyses of the DS2B, including differential/linear cryptanalysis, bijective, nonlinearity, strict avalanche criterion (SAC), and bit independence criterion (BIC) have been presented where high nonlinearity, and low differential uniformity are achieved. Besides, a comparison with recent S-boxes is introduced which shows the robustness of the DS2B. To verify the DS2B, a speech encryption engine was realized on FPGA. Various security analyses were evaluated including the National Institute of Standards & Technology (NIST) statistical test suite, number of samples changes rate NSCR, mean square error (MSE), correlation, histogram, and spectrogram. In this work, the silence periods are encrypted in a way that makes them much harder to detect using the DS2B. The proposed encryption scheme achieved a throughput of 9.87 G bit/s, which is higher than previous work. A Xilinx Nexys 4 FPGA evaluation board was used for implementing and verifying the design.

Highlights

  • The security of IoTs continues to attract the attention of researchers due to their pervasive nature

  • PROPOSED DS2B METHOD This paper presents a method for obtaining dynamic and secure S-Box (DS2B) to be used in a speech encryption application

  • EXPERIMENTAL RESULTS The proposed encryption design was realized on Nexys 4 FPGA device XC7A100T, package CSG324, and tested as follows: All the speech files were stored in text files by using the MATLAB software

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Summary

Introduction

The security of IoTs continues to attract the attention of researchers due to their pervasive nature. Implementing security algorithms on edge devices is a highly challenging task as they tend to have limited computation capability, small memory, and small power budget [1]. The projection of fifty Billion Internet-of-Things (IoT) devices by 2020 has pushed the energy harvesting research to study new solutions for improving the lifetime of batteries [2], [3]. The optimization of hardware implementation of IoT cryptographic engines is of paramount importance to address the issues of cost, throughput, and power budget. Most existing encryption designs for low-cost and low-power systems focus on optimizing the S-box, which has a significant effect on the area and energy cost [4], [5].

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