Dry Etching of Metal Inserted Poly-Si Stack for Dual High-k and Dual Metal Gate Integration

Abstract

Dry etching of AlN or TaN barrier layer/Mo stack (pMOS) and TaN (nMOS) in metal inserted poly-Si stacks structure for dual high-k and dual metal gate integration are investigated in detail. Firstly, in order to get a vertical profile, smooth etched surface and low Si loss, the optimal BCl3/O2/Ar plasma is developed for the etching of AlN/Mo stack. After that, both the optimal BCl3/Cl2/O2/Ar and BCl3/SF6/O2/Ar plasma are developed for the etching of TaN and TaN/Mo stack. Then, the TaN/Mo stack is chosen as the final pMOS structure since nMOS TaN metal gate will get a tapered profile under the optimal etching condition of AlN/Mo. Moreover, optimized BCl3/SF6/O2/Ar plasma is adopted for the etching of TaN and TaN/Mo stack simultaneously with both a vertical profile and a higher selectivity to the underlying layer. Finally, good electrical characteristics of CMOS device, obtained by utilizing the new developed technology, further prove that it is a practicable technology for the dual high-k and dual metal gate integration.