Dry etch sequencing induced gate oxide degradation due to metallic contamination in 0.25 μm CMOS manufacturing

Abstract

To ensure maximum tool utilization in high volume semiconductor manufacturing, multiple etch recipes may be implemented on a given etch chamber configuration. Due to the increased process complexity required for 0.25 /spl mu/m semiconductor fabrication, residual effects in chambers and interaction between etch recipes can change individual etch process outputs. Described below is 40 /spl Aring/ gate oxide degradation due to residual metallic contamination in an etch chamber caused by a previous contact etch process, in high volume 0.25 /spl mu/m CMOS manufacturing. Chamber seasoning, the specific combination of etch processes run due to product needs, post-etch cleans, and gate polysilicon doping all have a significant effect on the degree of oxide degradation caused. Also discussed is the impact of the degraded oxide on circuit yield and reliability.