Dry Etch Process Effects on Cu/low-k Dielectric Reliability for Advanced CMOS Technologies

Abstract

Cu and low-k dielectric based back-end-of-the-line (BEOL) interconnects is indispensable in advanced CMOS technologies for its significant improvement of chip resistance-capacitance (RC) delay. In this paper, we investigate the effects of dry etch process on the reliability of copper interconnects such as electromigration (EM), time dependent dielectric breakdown (TDDB) and stress migration (SM). Both the via height of its vertical part and the bevel profile of via isolation in dual damascene (DD) structure are detected to remarkably impact the final EM performance. Main contributors for TDDB include the low-k sidewall damage from ash, the interface necking right after the diluted HF (DHF) wet owing to insufficient sidewall passivation and the bowling profile from non-optimized integration process. EM enhancement related profiles are usually associated with smaller line top critical dimension (CD). This might degrade TDDB performance. We proposed the optimized etch method to address this trade-off issue. SM performance is normally defined by the mechanical and thermal properties of copper interface in DD structure. It can also be improved in etch process by post etch scheme such as N2/H2 treatment from the point view of polymer residue removal and copper interface repair.