Dry etch challenges of 0.25 /spl mu/m dual damascene structures

Abstract

Interconnects for integrated circuits are generally formed by reactive ion etching (RIE) of the metal stack. However, this process is susceptible to shorts between neighboring lines due to either incomplete etching of the stack or electrically conducting etch by products. As a result, there has been much recent interest in using damascene processes (where chemical-mechanical polishing (CMP) is used to form the metal lines) to fabricate interconnects at dimensions of 0.25 /spl mu/m and less. The damascene process has a number of benefits; the lines are defined by oxide RIE, which is considerably simpler than RIE of a multilayer metal stack. The metal CMP process provides a nearly planar surface, eliminating the need for good gap fill by the interlevel dielectrics. Finally, the metal fill of the interconnects and vias can be combined into one step (i.e. dual damascene), resulting in reduced cost.