Dry and Wet Processed Interface Layer in Ge/High-K Devices Studied by Deep Level Transient Spectroscopy

Abstract

In this work, dry and wet processed interface layer quality in Ge/High-K MOS structure (1) were studied by deep level transient spectroscopy (DLTS) (2). The MOS devices were pulsed from mid-bandgap to accumulation region, then return to mid-bandgap to obtain the majority carrier trap emission information. Figure 1(a-c) shows the DLTS data for three corresponding interface treatment. The Arrhenius plots are shown in Figure 1(d). Comparing the DLTS spectrum, it can be concluded that dry processes have discrete border traps at the interface (H3 and H5). No such traps at the interface of wet processed MOS devices were observed. For all three samples, however, interface like traps were detected (H1, H2, H4). The defects density was estimated by Eq. (1), where is obtained from CV plot using measured . The results suggest that it is around 1013 cm-2/eV for all three samples. This further confirms that the origin of interface state density, Ditobserved for these samples (1) are mainly due to these traps. The time constants in the order of milliseconds were also previously observed. Table I summarizes the Energy levels and cross-sections of these traps. (1) Acknowledgement:The authors would like to thank K. Tapily, R. D. Clark, S. Consiglio, C. S. Wajda, and G. J. Leusink of TEL Technology Center, Albany, NY, for supplying devices and helpful discussions. Table I. Arrhenius plot fitting results H1 H2 H3 H4 H5 ET-EV (eV) 0.16 0.1 0.18 0.04 0.45 (cm2)a 6.3×10-17 1.3×10-19 3.6×10-19 5.8×10-21 8.6×10-13 a Cross section is calculated by assuming = 1020 cm-2 s-1K-2. Figure 1. Deep level transient spectrum of (a) simple chemical oxidation (Chemox), (b) chemical oxide removal (COR) followed by 1 nm oxide by slot-plane-antenna (SPA) plasma (COR&SPAOx), (c) COR followed by vapor O3 treatment (COR&O3). (d) shows the Arrhenius plots for all three samples.