Abstract
Digital Microfluidic Biochip (DMFB) is a revolutionary technology for performing lab-on-a-chip experiments. Comparing to traditional direct-addressing design of DMFB, Cross-Referencing Biochip is a flexible design which not only helps to reduce pin number on chip but also brings down manufacturing cost. Following the generally accepted DMFB top-down design methodology, namely task scheduling, resource binding, module placement, droplet routing, previous works that focus on cross-referencing biochip routing are all based on the placement result generated for direct-addressing biochip. In this paper, we present an ILP-based placement method that first utilizes the property of cross-referencing for the purpose of optimizing routing. Furthermore, one previously ignored electrode interference problem on modules (blocks) is addressed in this paper. Real-life bioassay protocol based benchmarks are used to evaluate the proposed method. Experimental results show that the placement result generated by our placer yields better routing result comparing with those from placer for direct-addressing DMFB.
Highlights
1.1 Digital Microfluidic BiochipDigital Microfluidic Biochip has been receiving more and more attention today [1]
Geometry-level synthesis is performed to generate the detailed layout of the chip, which includes the module placement and droplet routing
We run the router on the placement generated by [15] and on the placements generated by our approach
Summary
Digital Microfluidic Biochip has been receiving more and more attention today [1]. It shows great advantages in medical, pharmaceutical and environmental monitoring applications [2]. Many tasks can be performed without using expensive equipment and human resource. Highly complicated computer-aided design support is strongly in demand for DMFB as in traditional VLSI design. Paper [4] introduced a novel top-down design methodology for DMFB. Architectural-level synthesis follows to generate the macroscopic structure of the chip, which contains the task scheduling and resource binding information. Geometry-level synthesis is performed to generate the detailed layout of the chip, which includes the module placement and droplet routing
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