Drop Test Simulation and DOE Analysis for Design Optimization of Microelectronics Packages

Abstract

For better drop performances, there have been significantly increased research works focusing on different levels (e.g. product- and board-level) of reliabilities for microelectronics packages. Many important factors have been considered in the recent experimental and numerical studies. The interactions between these factors, e.g. sizes, materials, and etc, however, are relatively unknown. Based on finite element modeling and design of experiment (DOE), a novel approach was discussed in detail to investigate the impacts of all possible key factors as well as their weights and interactions on the dynamic responses of over-molded LGA (land grid array) RF packages. Molding compound, solder, and substrate materials, as well as the dimensions of die, die attach (DA), and solder layer, were considered to reduce the critical interfacial peeling stress so that an optimized design can be achieved. The DOE model was set-up through 3D full parametric modeling from which every key factor can be adjusted easily. Each DOE leg is a drop test simulation equivalent to JEDEC standard drop which has 1500g peak acceleration and 1 ms impulse duration. The simulations were conducted through LS-DYNA explicit finite element analysis and the DOE analyses were carried out through JMP. The experiment record of acceleration vs. time was input as load and constrain on the base plate of the drop test vehicle. Two rounds of DOE and totally 20 drop simulations were carried out to deliver the valid analysis. The first round is a screening DOE to identify the most important 3/spl sim/4 factors. Then a full factorial DOE was carried out to study these key factors and their interactions. The final results could be used as a design guideline to improve the drop performance of microelectronics packages.