Abstract
The development of current and future broadband access techniques into the wireless domain introduces new and flexible network architectures with difficult and interesting challenges, e. g. access mechanisms, energy conservation, error rate, transmission speed characteristics of the wireless links and mobility aspects. This paper discusses first the major challenges in hardware architecture design of reconfigurable system-on-a-chip solutions for the digital baseband processing in future mobile radio devices. The focus of the paper is the introduction of a new dynamically reconfigurable hardware architecture tailored to this application area. Its performance issues and potential are discussed by the implementation of a flexible and computation-intensive component of future mobile terminals.
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