Abstract
The simulation of Dynamic Random Access Memories (DRAMs) on system level requires highly accurate models due to their complex timing and power behavior. However, conventional cycle-accurate DRAM subsystem models often become a bottleneck for the overall simulation speed. A promising alternative are simulators based on Transaction Level Modeling, which can be fast and accurate at the same time. In this paper we present DRAMSys4.0, which is, to the best of our knowledge, the fastest and most extensive open-source cycle-accurate DRAM simulation framework. DRAMSys4.0 includes a novel software architecture that enables a fast adaption to different hardware controller implementations and new JEDEC standards. In addition, it already supports the latest standards DDR5 and LPDDR5. We explain how to apply optimization techniques for an increased simulation speed while maintaining full temporal accuracy. Furthermore, we demonstrate the simulator’s accuracy and analysis tools with two application examples. Finally, we provide a detailed investigation and comparison of the most prominent cycle-accurate open-source DRAM simulators with regard to their supported features, analysis capabilities and simulation speed.
Highlights
Since today’s applications become more and more data centric, the role of Dynamic Random Access Memory (DRAM) in compute platforms grows in importance due to its large impact on the whole system performance and power consumption
In addition to the original work, we show two application examples that demonstrate the flexibility of DRAMSys4.0
To show the relative performance improvement that is achieved with faster DDR4 speed grades and different DDR5 speed grades the Instructions Per Cycle (IPC) is normalized to the slowest memory (DDR4-1600)
Summary
Since today’s applications become more and more data centric, the role of Dynamic Random Access Memory (DRAM) in compute platforms grows in importance due to its large impact on the whole system performance and power consumption. A short time to market aggravates this choice and creates the need for DRAM simulation models that allow both fast and truthful design space exploration. A DRAM subsystem simulation represents one specific JEDEC standard, and only one specific controller implementation. This simulation can be performed on several levels of abstraction, each offering a certain trade-off between speed and accuracy.
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