Drain Bias Effect on the Instability of Amorphous InGaZnO Thin-Film Transistors under Negative Gate Bias and Illumination Stress

Abstract

The effect of drain bias (V DS) on the negative gate bias and illumination stress (NBIS) stability of amorphous InGaZnO (a-IGZO) thin-film transistors was investigated using a double-sweeping gate voltage (V GS) mode. The variation in the transfer characteristics was explored using current–voltage and capacitance–voltage characteristics. In the initial stage (<1000 s) of NBIS with V DS of 40, 0, and −20 V (V GS = −40 V and V DS > V GS), the transfer characteristics shifted negatively with an insignificant change in the subthreshold swing (SS) due to hole trapping at an IGZO/gate insulator interface. In the subsequent stage (>1000 s), on-current degradation was observed and was accelerated in the forward measurement as the NBIS duration increased. The enhanced and weakened degradations were respectively observed by applying V DS of 40 and −20 V compared with grounded V DS. The transfer curves in the reverse measurement shifted positively without on-current and SS degradations, which were well described by the stretched-exponential equation. Furthermore, it was confirmed that the NBIS degradations could be suppressed by applying a large negative V DS bias of V DS < V GS (V GS = −40 V and V DS = −60 V) during NBIS.