Double tunnel junctions for magnetic random access memory devices

Abstract

Optimum junction resistance and minimum tunnel magnetoresistance (TMR) ratio required for high density and high performance magnetoresistive random access memory (MRAM) devices with a TMR cell plus field effect transistor (FET) switch architecture are discussed by taking into account the variation of FET resistance causing noise. This implies that a TMR ratio over 25% at a 400 mV bias voltage and junction resistance of several tens of kilo-ohms for TMR cells are required with a signal voltage of 30 mV and a sense current of 10 μA, which leads to about 10 ns read time. This large magnetoresistance ratio at the elevated bias voltage requires low bias voltage dependence of TMR for the MRAM devices. In order to try to meet this requirement, double tunnel junctions were fabricated which possess the central ferromagnetic layer consisting of a thin discontinuous layer of hard ferromagnetic Co80Pt20 nanoparticles and insulating Al2O3 prepared by alternate sputtering of Co80Pt20 and Al2O3 targets. The maximum TMR obtained was 20.5% at room temperature for FeCo top and bottom electrodes without annealing. Bias voltage dependence of the (NiFe/CoFe)/1.5 nm Al2O3/discontinuous CoPt/2.6 nm Al2O3/(CoFe/NiFe) double tunnel junctions were revealed to be small compared to that of single junctions, the barrier of which was also fabricated by sputtering of an Al2O3 target.