Double span floating point representation scheme for the powers-of-two filter

Abstract

The area of signal processing has been experiencing silent revolution over the last few years. A number of promising algorithms are being developed in this regard. In connection to this, minimization of hardware complexity of digital filter has grown sufficient interest amongst the research community. Hardware cost of digital filter may be reduced by encoding the filter coefficient in the form of sum of signed powers-of-two (SPT). This article introduces a new encoding strategy of the non-uniform powers-of-two coefficients for the sake of exploiting minimum hardware units. Proposed scheme targets to minimize the highest powers-of-two terms in any coefficient by judiciously dividing the ‘span’ part into two segments. As a matter of fact, it necessitates the use of minimum number of full-adder blocks during implementation as compared to other existing coefficient representation schemes. Supremacy of the proposed double span floating point (DSFP) representation technique has been mathematically substantiated and supported with the help of few design examples.