Abstract
We have developed a double-recessed 0.1-µm-gate InP-based high electron mobility transistor (DR-HEMT). In this double-recessed-gate structure, the outer-recessed width and the inner-recessed depth are very important in terms of the device characteristics. In order to suppress the maximum electric field strength within the channel region and to reduce the source resistance (Rs), we have performed a device simulation and have obtained the optimum double-recessed gate structure. The DR-HEMT shows a good transconductance over drain conductance gain (gm/gd) of 26 and a high maximum oscillation frequency (fmax) of 351 GHz because of the improved gd with a small Rs. The propagation delay (tpd) of a source-coupled field effect transistor logic (SCFL) inverter implemented by DR-HEMTs is as fast as 5.8 ps/gate. We have applied the DR-HEMT technology to a static 1/2 frequency divider and obtained stable operation up to 43 GHz.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
