Double quantum-well nanotube tunneling field-effect transistor

Abstract

In this paper, a double quantum-well nanotube tunneling field-effect transistor is introduced. In order to provide higher scalability, we utilize the core-shell gate architecture. The dominant transport mechanism in our device is in-line tunneling of charge carriers from a germanium source region to two silicon quantum-wells, which are located at the opposite sides of the source and separately controlled by the gates. We show that the fabrication process flow of the proposed device is CMOS-technology compatible. A numerical device simulator, that is calibrated to measured data of a fabricated Ge-source NW TFET, is employed to realistically investigate the switching and analog characteristics of the device. According to the obtained results, our device exhibits an Ion/Ioff ratio of 2.85 × 109, an on-state current of 38.73 μA/μm, a minimum subthreshold swing of 2mV/dec, and a cut-off frequency of 44.7 GHz. We also show that with a slight modification of the device structure, in exchange for a negligible reduction of on-state current, the Ion/Ioff ratio can reach to ∼1011 and ambipolarity vanishes considerably.