Double patterning in lithography for 65nm node with oxidation process

Abstract

Recently, in order to increase the number of transistors in wafer by small feature size, optical lithography has been changed to low wavelength from 365nm to 193nm and high NA of 0.93. And further wavelength is aggressively shifting to 13.5nm for more small feature size, i.e., Extreme Ultra Violet Lithography(EUVL), a kind of Next Generation Lithography(NGL)¹. And other technologies are developed such as water immersion(193nm) and photo resist Double Patterning(DP). Immersion lens system has high NA up to 1.3 due to high n of water(n=1.44 at 193nm), the parameter k1 is process constant, but 0.25 is a tough limit at a equal line and space, if we use immersion lens with 193nm wavelength than limit of resolution is 37nm. Especially, Double Exposure Technique(DET) process is widely studied because of the resolution enhancement ability using a same material and machine, despite of process complication. And SADP(Self Aligned Double Patten) is newly researched for overlay and LER(Line Edge Roughness) enhancement. In this paper, we illustrate the feasibility of the shift double pattern for 65nm-node flash using a 193nm light dipole source and the possibility of decrease minimum feature size using a property of silicon shrinkage during thermal oxidation process.