Double Modular Redundancy (DMR) Based Fault Tolerance Technique for Combinational Circuits

Abstract

Due to the continuous scaling of digital systems and the increased demand on low power devices, design of effective soft error tolerance techniques is of high importance to cope with the increased susceptibility of systems to soft errors and to enhance system reliability. In this work, we propose a double modular redundancy (DMR) technique that aims to achieve high reliability with reduced area overhead. Furthermore, we propose an improved application of DMR based on the use of C-element (DMR-CEL). The proposed technique is compared with Triple Modular Redundancy (TMR) technique and DMR-CEL. Simulations performed for LGSynth’91 benchmark circuits demonstrate that applying the proposed DMR technique achieves improved reliability with significantly lower area overhead than TMR without voter protection. Furthermore, improved reliability with lower area overhead is achieved by the proposed DMR technique in comparison to DMR-CEL without C-element protection. In addition, applying a recently proposed transistor sizing technique on our proposed DMR technique achieves comparable reliability to that achieved by TMR with voter protection and DMR-CEL with C-element protection with lower area overhead than TMR.