Double gate silicon-on-insulator transistors: n/sup +/-n/sup +/ gate versus n/sup +/-p/sup +/ gate configuration

Abstract

We have studied electron mobility behavior in asymmetric double-gate silicon on insulator (DGSOI) inversion layers, and compared it to the mobility in symmetric double-gate silicon on insulator devices. The electron mobility curves in asymmetric DGSOI devices are shown to be considerably below the mobility curves corresponding to symmetric devices, in the whole range of silicon thicknesses. We show that the lack of symmetry in the asymmetric DGSOI structure produces the loss of the volume inversion effect. In addition, we show that as the silicon thickness is reduced, the conduction effective mass of electrons in asymmetric devices is lower than that in the symmetric case, but that the greater confinement of electrons in the former case produces a stronger increase in the phonon scattering rate, and in the surface roughness scattering rate.