Abstract

In this paper a novel graphene nanoribbon transistor with electrically induced junction for source and drain regions is proposed. An auxiliary junction is used to form electrically induced source and drain regions beside the main regions. Two parts of same metal are implemented at both sides of the main gate region. These metals which act as side gates are connected to each other to form auxiliary junction. A fixed voltage is applied on this junction during voltage variation on other junctions. Side metals have smaller workfunction than the middle one. Tight-binding Hamiltonian and nonequilibrium Green's function formalism are used to perform atomic scale electronic transport simulation. Due to the difference in metals workfunction, additional gates create two steps in potential profile. These steps increase horizontal distance between conduction and valance bands at gate to drain/source junction and consequently lower band to band tunneling probability. Current ratio and subthreshold swing improved at different channel lengths. Furthermore, device reliability is improved where electric field at drain side of the channel is reduced. This means improvement in leakage current, hot electron effect behavior and breakdown voltage. Application to multi-input logic gates shows higher speed and smaller power delay product in comparison with conventional platform.

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