Double fundamental frequency PLL with second order generalized integrator under unbalanced grid voltages

Abstract

Under unbalanced grid voltage conditions, negative-sequence will generate the double fundamental frequency in the dq synchronous rotating reference frame. In order to detect the positive-sequence component of the grid voltages fast, this paper proposes a new phase-locked loop method, called double fundamental frequency phase-locked loop (DFF-PLL). The operation principle is analyzed, giving the extract formulas of the positive- and negative-sequence with double fundamental frequency, the process of DFF-PLL and the detection of positive-sequence component of grid voltages. The paper improves the second order generalized integrator quadrature-signals generation (SOGI-QSG), in order to remove the DC bias voltage and guarantee the orthogonality of SOGI-QSG. The performance of DFF-PLL is verified by using simulation and experimental results. Compared with DSOGI-PLL, this method increases the detection speed and accuracy under unbalanced grid voltage conditions.