Double-delay fractional and integer-order tanlock loops

Abstract

Double-delay tanlock loops with fractional and integer-order filters that are straightforward to implement are proposed. The amplitude, phase and frequency of the input signal are explicitly obtained with the aid of two delayed signals. Two types of loops are proposed: direct locking loop, where locking is achieved in a single sample but the loop does not have a filter, and an iterative locking loop, where locking is achieved using an integral iterative action. The iterative loop implements a filter, which governs the rate of locking and filters out unwanted noise. The iterative loop exhibits an attractive linear phase error detector with a period of 2 π . Convergence and locking range analyses of first- and second-order loops are introduced. The loops with two time delays are not affected by the variation in signal power and have a wide locking range. The fractional-order dynamics of the digital loop filter increase the loop bandwidth which increases its bandwidth but makes it susceptible to noisy signals. A fifth-order loop filter can approximate an infinite dimensional fractional-order filter which can easily be implemented using existing fast DSP processors. The main points of this work are illustrated via numerical simulation.