Doping-free complementary WSe2 circuit via van der Waals metal integration

Lingan Kong,Weiqi Dang,Mingliang Zhang,Quanyang Tao,Yuan Liu,Liping Feng,Xiangfeng Duan,Lei Liao,Xiaodong Zhang,Zhiwei Li

doi:10.1038/s41467-020-15776-x

Abstract

Two-dimensional (2D) semiconductors have attracted considerable attention for the development of ultra-thin body transistors. However, the polarity control of 2D transistors and the achievement of complementary logic functions remain critical challenges. Here, we report a doping-free strategy to modulate the polarity of WSe2 transistors using same contact metal but different integration methods. By applying low-energy van der Waals integration of Au electrodes, we observed robust and optimized p-type transistor behavior, which is in great contrast to the transistors fabricated on the same WSe2 flake using conventional deposited Au contacts with pronounced n-type characteristics. With the ability to switch majority carrier type and to achieve optimized contact for both electrons and holes, a doping-free logic inverter is demonstrated with higher voltage gain of 340, at the bias voltage of 5.5 V. Furthermore, the simple polarity control strategy is extended for realizing more complex logic functions such as NAND and NOR.

Highlights

Two-dimensional (2D) semiconductors have attracted considerable attention for the development of ultra-thin body transistors
With the ability to control the polarity of WSe2 transistors and to achieve optimized contact to both PMOS and NMOS using the same metal, a logic inverter is demonstrated with the highest voltage gain of 340 and total noise margin over 90%
In summary, we have demonstrated a doping-free strategy to control the polarity of 2D transistors using the same contact metal Au and the same channel material WSe2, but different metal integration methods

Summary

Introduction

Two-dimensional (2D) semiconductors have attracted considerable attention for the development of ultra-thin body transistors. We report a doping-free strategy to achieve CMOS circuit functions by using the same contact metal gold (Au) and the same channel material WSe2, but different metal integration methods. By applying low-energy van der Waals (vdW) integration of Au electrode, we observed a robust and consistent ptype behavior in multilayer WSe2 This is in great contrast to the transistors fabricated on the same WSe2 flake using conventional deposited Au contacts, where pronounced n-type characteristic is always observed[26,27]. With the ability to control the polarity of WSe2 transistors and to achieve optimized contact to both PMOS and NMOS using the same metal, a logic inverter is demonstrated with the highest voltage gain of 340 (at a bias voltage of 5.5 V) and total noise margin over 90%. Our results demonstrate robust and high-performance CMOS logic circuit using vdW metal electrodes, and provide a doping-free method to control the polarity of a 2D semiconductor using the same contact metal, shedding light to high-performance 2D electronics and CMOS design

Methods

Results

Conclusion