Abstract
This article describes at-speed IC testing which is critical to product quality. At nanometre geometries, many companies now require the application of at-speed patterns in order to improve defect detection and reduce DPM. Consequently, test application time and test data volume have dramatically increased thus turning test into a very costly portion of the overall product cost. For today's nanometre designs, compression of test time and data volume is essential to solve these problems and keep test cost within reasonable limits. New at-speed and compression techniques, presented in this article, enable companies to maintain high test quality of their nanometre designs and to ensure profitability remains unaffected by rising test costs.
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