Domino logic synthesis using complex static gates

Abstract

We address the synthesis of the most general form of a domino gate (dynamic-static domino), which consists of the pairing of a dynamic gate with any inverting static gate. All previous work focused on the synthesis of the most basic domino gate (standard domino), where the inverting static gate is an inverter. We developed a methodology and tools for synthesizing random logic blocks using both dynamic and complex inverting static gates in an alternating fashion. Dynamic-static (DS) domino can be used to reduce both gate levels and clock loading compared to standard domino. Comparisons between DS domino, standard domino, and static CMOS logic families are provided for six MCNC combinational logic benchmark circuits. Spice simulations show DS domino to have an average speed improvement of 53% over static CMOS and an average speed improvement of 17% over standard domino. DS domino also reduced clock loading by an average of 48% over standard domino. The paper introduces DS domino and presents a methodology for synthesizing random logic circuits using DS domino and other monotonic logic families such as Zipper CMOS.