Dominant SILC mechanisms in HFO/sub 2/TiN gate nMOS and pMOS transistors

Abstract

To introduce high-k dielectrics into conventional CMOS product flow, reliability issues of high-k gate stacks need to be addressed. Although several studies have focused on this issue, the physical mechanism of stress-induced degradation in high-k dielectrics is still not clear. In SiO/sub 2//poly-Si gate stacks, most intrinsic degradations are attributed to trap generation leading to the percolation model type failure, while pre-existing defects are believed to contribute to extrinsic mode failure (Olivio, P. et al., 1988). For the HfO/sub 2//TiN gate stack, it has been reported that a similar mechanism was at work (Crupi, F. et al., 2004). However, considering the high density of pre-existing electron traps (Zhan, N. et al., 2003) and the time dependent reversible threshold voltage shift (Lee, B.H. et al., 2004), one may expect that the electron accumulation in the dielectric during electrical stress may cause the modulation of the energy barrier and affect the electron tunneling, which, in turn, may lead to variation of SILC with the stress time. We have investigate the SILC characteristics of HfO/sub 2//TiN gate nMOS and pMOS transistors in conjunction with the trapping/detrapping processes in the high-k dielectric.