Domain-wall shift based multi-level MRAM for high-speed, high-density and energy-efficient caches

Abstract

Spin Transfer Torque (STT) Magnetic Random Access Memory (MRAM) is a promising candidate for future on-chip memory, owing to its attractive features like non-volatility, high-density, and zero-leakage [1, 2]. However, the speed and reliability of the standard MRAM cell (1Transistor-1Resistor or 1T-1R cell shown in Fig. 1), are mainly limited by dielectric breakdown of the magnetic tunnel junction (MTJ) [1] under high write-current injection [3, 8] (Fig. 2). In recent years, several device solutions have been proposed that can mitigate this bottleneck by employing separate read and write paths, thereby avoiding write-current injection into the tunneling oxide. Nonlocal-STT [4], Spin-Hall Effect [5], and domain-wall-shift (DWS) [6-8] are three such write mechanisms. We have observed that DWS can be highly energy-efficient and robust, owing to low-voltage, low-current magnetization switching and high cell TMR (tunnel magneto-resistance ratio [1]) [4-6]. However, such bit-cells, with isolated read and write ports, are bound to use two access transistors (Fig. 3), resulting in significant area-penalty. In this work, we propose a multi-level MRAM (ML-MRAM) bit-cell based on DWS that can store 2-bits of data per-cell and can therefore achieve a factor of ~2x reduction in area, read latency as well as read energy (which dominates the total energy consumption) as compared to a DWS-based single-bit-cell. The proposed bit-cell can outperform the standard 1T-1R MRAM (Fig. 1), by a factor of ~2x in terms of area, read-latency, read-energy and by 8x and 4x in terms of write-energy and read disturb margin respectively, apart from mitigating the reliability issues related to dielectric-breakdown. Due to the possibility of sub-nano-second read/write operations, the proposed multi-level bit-cell can be suitable for all levels of the cache hierarchy, including L1 caches (in contrast, previous MRAM proposals have focused on the lower-level caches, which have less stringent speed requirements).