Domain-Specific Modeling and Optimization for Graph Processing on FPGAs

Abstract

The use of High Level Synthesis (HLS) tools is on the rise; however, performance modelling research has been mainly focused on regular applications with uniform memory access patterns. These performance models fail to accurately capture the performance of graph applications with irregular memory access patterns. This paper presents a domain-specific performance model targeting graph applications synthesized using HLS tools for FPGAs. The performance model utilizes information from the hardware specification, the application’s kernel, and the graph input. While the compilation process of HLS tools takes hours, the information required by the performance model can be extracted from the intermediate compilation report, which compiles in seconds. The goal of this work is to provide FPGA users with a performance modelling framework for graph applications, to estimate performance and explore the optimization space. We tested the framework on Intel’s new Devcloud platform and achieved speedup up to $$3.4\times $$ by applying our framework’s recommended optimization strategy compared to the single pipeline implementation. The framework recommended the best optimization strategy in 90% of the test cases.