Abstract
SummaryTo overcome the challenges of energy consumption of HPC systems, the European Union Horizon 2020 READEX (Runtime Exploitation of Application Dynamism for Energy‐efficient Exascale computing) project uses an online auto‐tuning approach to improve energy efficiency of HPC applications. The READEX methodology pre‐computes optimal system configurations at design‐time, such as the CPU frequency, for instances of program regions and switches at runtime to the configuration given in the tuning model when the region is executed. READEX goes beyond previous approaches by exploiting dynamic changes of a region's characteristics by leveraging region and characteristic specific system configurations. While the tool suite supports an automatic approach, specifying domain knowledge such as the structure and characteristics of the application and application tuning parameters can significantly help to create a more refined tuning model. This paper presents the means available for an application expert to provide domain knowledge and presents tuning results for some benchmarks.
Highlights
Energy efficiency and consumption have become the most important and challenging issues in current HPC systems and in designing future exascale computing systems.[1]
The evaluation of Design Time Analysis (DTA) using domain knowledge was performed on three applications: Multi-Grid (MG),[9] Block Tri-diagonal solver (BT-MZ),[9] and ESPRESO.[10,19,20]
MG and BT-MZ, which are from the NAS Parallel Benchmarks suite, are derived from computational fluid dynamics (CFD) applications.[21]
Summary
Energy efficiency and consumption have become the most important and challenging issues in current HPC systems and in designing future exascale computing systems.[1]. Optimized system configurations can be configured for dynamic variation in characteristics of the program's execution, such as the compute intensity. READEX leverages the hardware features for Dynamic Voltage and Frequency Scaling (DVFS) of the Intel Haswell processor family that allows the userspace governor to set the frequency for individual cores as opposed to full sockets as seen in previous processor lines. The frequency of the uncore chip area can be tuned in the Haswell processor independent of the core frequency.[4] The frequencies can be controlled by setting machine specific registers (MSRs)
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