Abstract
AbstractWhile trace cache, value prediction, and prefetching have been shown to be effective in the single-threaded superscalar, there has been no analysis of these techniques in a Simultaneously Multi threaded (SMT) processor. SMT brings new factors both for and against these techniques, and it is not known how these techniques would fare in SMT. We evaluate these techniques in an SMT to pro vide recommendations for future SMT designs. Our key contribu tions are: (1) we identify a fundamental interaction between the techniques and SMT’s sharing of resources among multiple threads, and (2) we quantify the impact of this interaction on SMT through put. SMT’s sharing of the instruction storage (i.e., trace cache or i-cache), physical registers, and issue queue impacts the effectiveness of trace cache, value prediction, and prefetching, respectively.KeywordsMultiple ThreadBlock CacheThroughput ImprovementValue PredictorInstruction StorageThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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