DÉJÀ VU: An Entropy Reduced Hash Function for VLSI Layout Databases

Abstract

Modern very large-scale integration (VLSI) layout databases routinely consist of 10e15 edges, and thus problems of information retrieval, intellectual property (IP) inventory control, tampering detection, IP infringement detection, data tagging, and database version control, are extremely computationally intensive. All these tasks can be reduced to the problem of copy detection, and in this paper, we propose a canonical hash function for VLSI layout datasets which can be used for efficient copy detection and signature generation. The proposed signature is independent of the ordering of the layout elements, their tessellation, resolution, and even vertex count. These parameters, which do not contribute to the final wafer image, increase the entropy of the data and thus standard hash functions such as message digest (MD5) or secure hash algorithm (SHA), are not suitable for this problem of VLSI layout hashing. In this paper, a novel, entropy reduced hash function is developed which can be used to alleviate the above mentioned problems of physical IP management. The proposed method has ${O(n \log n + k)}$ time complexity, and $ {O(\sqrt {n})}$ memory complexity, where $ {n}$ is the number of edges in the input layout, and $ {k}$ is the number of intersections between edges. The proposed system has been implemented, and computational results validating our approach are also provided.