Divide and conquer algorithm for parallel reconfiguration of VLSI array with faults

Abstract

Although many reconfiguration strategies for fault tolerance on VLSI arrays have been proposed in the last two decades, few works on parallel reconfiguration have been reported. This paper presents an algorithm based on divide and conquer strategy for parallel reconfiguration VLSI arrays in the presence of faulty processing elements (PEs). The proposed algorithm splits the original host array into many sub-arrays in a recursive way, then target arrays are formed on each sub-arrays in parallel using a previous algorithm named GCR. The final target array is achieved by merging all these target arrays constructed on each sub-arrays. Experimental results show that the reconfiguration is significantly accelerated in comparison with previous algorithm GCR.