Abstract
In this article, we propose a novel architecture for single-flux-quantum (SFQ) circuits. It is compatible to the existing synchronous and asynchronous timing schemes and reduces the hardware cost for implementing the pipeline blocking and flushing, which are the two methods to improve the performance of SFQ microprocessors. We simulate two crucial elements, and the functions of the elements are verified successfully. The proposed architecture simplifies the logic design of the circuits, and it can be considered as a general architecture for SFQ circuits because of the compelling characteristics.
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