Distributed Pinning Spot Model for High-k Insulator - III-V Semiconductor Interfaces

Abstract

III-V metal-insulator-semiconductor (MIS) structures are recently attracting attentions as possible candidates of high-k gate stack for next generation CMOS transistors on the silicon platform. However, their basic electrical properties are not well understood. In order to further confirm the validity of the recently proposed distributed pinning-spot (DPS) model for anomalous admittance behavior of III-V MIS structures, we have carried out in this paper a detailed experimental and computer simulation study of a HfO2/GaAs high-k MIS structure controlled by a silicon interface control layer (Si ICL). It is clearly shown that the measured frequency dependences of C-V curves and admittance are far away from the predictions by the standard Si MOS theory. On the other hand, they can be well reproduced by the DPS model which assumes random spatial distribution of pinning spots with high densities of interface states in addition to pinning-free regions with low interface state densities. The model indicates that use of low-dimensional structures such as nanowires and nanodots may be beneficial for removal of pinning spots. [DOI: 10.1380/ejssnt.2009.122]