Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation

Abstract

Digital low-dropout regulators (DLDOs) have been drawing significant attention within modern integrated systems such as processors and Internet of Things (IoT) devices. Despite the advantages of low design complexity, low voltage operation capability, and fast transient response, the inherent limit cycle oscillation of DLDOs lead to undesirable output voltage ripple at steady state. On the other hand, distributed on-chip voltage regulation with multiple tiny voltage regulators distributed across the chip achieves superior on-chip voltage noise profile. In this work, distributed DLDOs with phase interleaving are exploited to mitigate on-chip voltage noise due to limit cycle oscillation. Resonant rotary clock (ReRoC) is leveraged for robust clock generation and distribution. It is demonstrated through theoretical analysis and extensive simulations that significant on-chip voltage noise reduction can be achieved with the proposed technique.