Distributed arithmetic-FIR filter design using Approximate Karatsuba Multiplier and VLCSA

Abstract

In this manuscript, a High Throughput and Low Latency DA-FIR filter design is integrated with Approximate Karatsuba Multiplier (AKM) and Variable Latency Carry Skip Adder (VLCSA) is proposed for the noise removal application in SDR. In this design, an AKM and VLCSA are considered to decrease the count of partial products on DA framework, although no multiplication is clearly performed. Thus, an important reduction is accomplished under accumulation circuits. The main execution problem of the DA system is the size of lookup table (LUT) increases exponentially through the length of inner product. To further diminish the memory complexity, approximate DA architectures depending truncation approach are needed. Partial products on DA are created through truncating least significant bits (LSBs) of inputs. The proposed hybrid technique lessens a count of LUTs by truncating the least significant bits of input operands. To further reduce the latency, this manuscript deals with one of the fastest multipliers, namely Approximate Karatsuba Multiplier employed for accumulation of partial products. The proposed design is performed in Verilog using Xilinx 14.5 ISE simulation. The experimental performances of the proposed DA-FIR-Hyb AKE-VLCSA filter is evaluated under lower delay, lower static power and compared with the existing filters.