Disposable polysilicon LDD spacer technology

Abstract

An advanced 0.5- mu m CMOS disposable lightly doped drain (LDD) spacer technology has been developed. This 0.5- mu m CMOS technology features surface-channel LDD NMOS and PMOS devices, n/sup +//p/sup +/ poly gates, 125-A-thick gate oxide, and Ti-salicided source/drain/gate regions. Using only two masking steps, the NMOS and PMOS LDD spacers are defined separately to provide deep arsenic n/sup +/ regions for lower salicided junction leakage, while simultaneously providing shallow phosphorus n/sup -/ and boron p/sup -/ regions for improved device short-channel effects. Additionally, the process allows independent adjustment of the LDD and salicide spacers to optimize the LDD design while avoiding salicide bridging of source/drain to gate regions. The results indicate extrapolated DC hot-carrier lifetimes in excess of 10 years for a 0.3- mu m electrical channel-length NMOS device operated at a power-supply voltage of 3.3 V. >