Dispatching schemes for Clos-network switches

Abstract

The Clos-network is widely recognized as a scalable architecture for high-performance switches and routers. The ATLANTA switch with its Memory/Space/Memory (MSM) architecture constitutes a commercially successful example. The CRRD and CMSD dispatching/arbitration algorithms have been recently proposed for the MSM Clos-network switches, by using simple round-robin arbiters. Based on the Static Round-Robin (SRR) technique, we propose the SRRD arbitration algorithm for the MSM Clos-network switches. The intuition behind the SRR technique is to desynchronize the pointers of the arbiters in a static way and hence considerably improve the delay performance. However, the MSM architecture is accompanied with a memory speedup problem. As a result, we propose a highly scalable Bufferless Clos-network switching architecture to address this issue. Based on the SRR technique again, we develop the Distro dispatching algorithm for the new architecture. We demonstrate by simulation that Distro can achieve 100% throughput under uniform traffic. The delay performance of Distro in the Bufferless Clos-network architecture is comparable to that of conventional algorithms in crossbar switches.