Disordered self assembled monolayer dielectric induced hysteresis in organic field effect transistors.

Abstract

A memory device using an organic field effect transistor (OFET) with copper phthalocyanine (CuPc) as active material was fabricated and studied. For this purpose, SiO2 dielectric surface was modified with a disordered self assembled monolayer (SAM) of octadecyltrichlorosilane (OTS) molecule which was found to induce large disorder in CuPc film thereby generating more traps for charge carriers. Drain current-drain voltage characteristics at zero gate voltage exhibited large hysteresis which was not observed in OFET devices with ordered OTS monolayer modified and unmodified SiO2 dielectrics. The extent of hysteresis and drain current on/off ratio, reading voltage etc. were found to be dependent on the sweep rate/step voltage employed during scanning. Highest hysteresis with on/off ratio of about 240 was obtained for an optimum step voltage of 2 V while it decreased with further reduction in the same. This was attributed to the longer scanning time leading to release of trapped carriers during forward scan itself. The OFET device was found to exhibit excellent memory retention capability where OFF and ON current measured for about 2 hours after stressing the device at write and erase voltages showed good retention of on/off ratio.