Abstract

This paper presents a design method for discrete-time parallel with continuous-time design for the n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> order plant employing PID (Proportional-Integral-derivative) times(n-2) stage PD as a cascade controller. The controller is designed to meet the transient and steady state response specifications via the root locus approach. The results revealed that, if the sufficient sampling time for discrete-time system is available, all desired specifications are easily obtained.

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