Abstract
Abstract : Computer architectures or instruction sets can be designed to be in close correspondence with high level computer languages. Techniques for designing this correspondence have been developed which produce instruction sets called Direct Correspondence Architectures, or DCAs. DCA representation minimize the number of bits needed to encode an instruction, as well as minimizing many of the dynamic parameters associated with program execution. In a Pascal-based DCA, the following reductions were achieved for a broad range of benchmarks when compared to a breadbasket of conventional architectures such as S/370, VAX, and P-code: 1) instruction bandwidth reduction: 3.46, 2) data read reduction (in bytes): 5.42, 3) data write reduction (in bytes): 14.72. A microprocessor based implementation of a Pascal-based DCA has begun. Issues in concurrency detection for these and other architectures have been investigated. Keywords include: Computer architecture, Instruction sets, instruction bandwidth, concurrent execution, direct correspondence architecture, directly executed languages. (Author)
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.