Abstract

With a 100 nm focus of a focused Ga+ ion beam with 100 keV, we write insulating lines in electronic layers of In0.21Ga0.79As quantum wells. In this way, in-plane-gate (IPG) transistors are formed which can be operated at room temperature. In a typical integration application of a common source circuit, the pull-up resistance represents a serious problem due to the high geometric aspect ratio necessary for it. For example, the typical specific sheet resistivity of the In0.19Ga0.79As quantum well of 1.2 kΩ needs to be increased to 100 kΩ by a 1 μm wide, about 83 μm long channel. In order to save this waste of area we introduce active loads in the form of a narrow channel. In this way, the pull-up resistor requires orders of magnitude less area and stabilizes the drain current due to velocity saturation, leading to lower supply voltages. Inverters in this technology are presented and characterized. In finite element simulations these circuits are further investigated. The operation of these systems is based on the lateral depletion of adjacent quantum well areas. The basic differences between depletion within pn half spaces and pn half planes are discussed analytically, showing a marked dependence on dimensionality. In particular, it is shown that the ruggedness of IPGs can be explained by these phenomena.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.