Abstract
The border traps, in particular slow border traps, are being investigated in metal-oxide-semiconductor structures, utilizing n-channel MOSFET as a test sample. The industrial process technology of test samples manufacturing is described. The automated experimental setup is discussed, the implementation of the experimental setup had made it possible to complete the entire set of measurements. The schematic diagram of automated experimental setup is shown. The charging time characteristic of the ID-VG shift reveals that the charging process is a direct tunnelling process and highly bias dependent.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
