Abstract
This paper investigates a potential application of microprogrammable memories to the problem of sequential network synthesis and computer design. It is shown that by allowing a controllable amount of memory redundance, a microprogrammed emulation of a state table can be organized such that decision branches in the microprogram are achieved in an immediate multiport manner, without the need of additional branch steps in the microprogram, thus increasing operational speed. A design technique is developed which, for a given state table, allows a minimum number of memory address variables to be used while minimizing the dependence of the variables on both the input and current state information. This technique has immediate practical application in the design of sequential networks, and is shown to be feasible in the controller design of a general purpost computer.
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